1. Field of the Invention
The present invention relates to the design of electronic circuits, and in particular, relates to the design of CMOS integrated circuits.
2. Discussion of Related Art
A reference bias current can be generating from the difference in the base-emitter voltages of two bipolar transistors of different current densities. One such reference bias current generation circuit is shown in FIG. 1. Referring to FIG. 1, reference bias current generation circuit 100 employs NPN bipolar transistors 102 and 104 to generate a reference bias current I.sub.ref which may be used to bias other circuits (not shown). In circuit 100, transistor 104 is designed to have a larger emitter area than does transistor 102 and, as a result, will thus exhibit a smaller current density than will transistor 102. P-channel MOS transistors 106 and 108 source equal currents to the respective collectors of transistors 102 and 104. Thus, when both transistors 102 and 104 are conducting in the linear region, a difference .DELTA.V.sub.BE between their base-emitter voltages results. The emitter terminal of transistor 104 is coupled to a current source 110 by a resistor 112. Thus, the current I.sub.ref generated by circuit 100 is determined by the resistance R of resistor 112, where I.sub.ref =.DELTA.V.sub.BE /R.
Another example of a reference bias current circuit is shown in FIG. 2. Reference bias current generation circuit 200 includes NPN bipolar transistors 202 and 204 which are designed to have different emitter areas and will thus exhibit different current densities. The emitter terminal of transistor 202 is coupled to a current source 206 by a resistor 208 having a resistance R. The emitter terminal of transistor 204 is coupled to current source 210. Current sources 206 and 210 are designed to sink substantially equal currents such that the emitter currents of transistors 202 and 204 are substantially equal.
In circuit 200, the voltage on node 212 (at the emitter terminal of transistor 204) and the voltage on node 214 are forced to be equal by the high gain of an operational amplifier 216, which provides a feedback signal at terminal 218 to control current sources 206 and 210. In equilibrium, the difference in base-emitter voltages of transistors 202 and 204 appears across resistor 208, where .DELTA.V.sub.BE =V.sub.be,Q202 -V.sub.be,Q204 =I.sub.ref R. Thus, the current I.sub.ref in each of current sources 206 and 210 is determined by the resistance R of resistor 208, where I.sub.ref =.DELTA.V.sub.BE /R. A current mirror can be used to generate a current equal to I.sub.ref or, in other embodiments, to any fraction or multiple of I.sub.ref.
In both of the prior art circuits discussed above, a reference bias current arising from the difference in base-emitter voltages of two bipolar transistors is generated by imposing such voltage difference across a resistor. However, if a small reference bias current is preferred, such a resistor would in an integrated circuit implementation require an unreasonably large amount of silicon real estate. For example, in circuit 200 of FIG. 2, if the emitter ratio between transistors 202 and 204 is 10:1, a .DELTA.V.sub.BE of approximately 60 millivolts is achieved. In such an implementation, providing reference currents I.sub.ref of 200 nanoamps and 60 nanoamps requires approximately 300 kilo-ohm and 1 Mega-ohm resistances R, respectively. Implementing such large resistances is uneconomical.
Alternatively, the resistor employed in the prior art circuits may be replaced by a field effect transistor (FET) operating in the non-saturation or "triode" region. Such an FET requires a much smaller silicon real estate than does a resistor conducting the same amount of current. However, the use of an FET has at least two disadvantages. First, the threshold voltage V.sub.T of such a transistor is known to vary substantially with variations in the manufacturing process. Consequently, the equivalent resistance attainable by such FET fluctuates with variations in the manufacturing process, thereby leading to large variations in the generated bias current. Secondly, the threshold voltage of such as FET is known to have a negative temperature coefficient. Consequently, the bias current generated by such an FET also has a negative temperature coefficient TC, which is undesirable for most amplifier applications.
FIG. 3 shows a reference bias current generating circuit 300 which overcomes the two disadvantages mentioned above by providing a matched reference transistor that tracks and effectively cancels process variations of the above mentioned FET such that the resistance of the FET is insensitive to process variations. Circuit 300 is described in detail in U.S. Pat. No. 5,469,111 issued to Kwok-Fu Chiu on Nov. 21, 1995 and assigned to National Semiconductor Corp, also the assignee of the present invention, hereby incorporated by reference.
Circuit 300 includes NPN transistors 302 and 304 which are designed to have different emitter areas and will thus exhibit different current densities. The emitter terminal of transistor 302 is coupled to a current source 308 by an NMOS transistor MN.sub.R having a resistance R. The emitter terminal of transistor 304 is coupled to a current source 310. Current sources 308 and 310 are designed to conduct substantially equal currents. Transistor MN.sub.R acts as a resistor in the reference bias current generation circuit 300, in that the difference .DELTA.V.sub.BE in base-emitter voltages of NPN transistors 302 and 304 appears across the drain terminal and the source terminal of transistor MN.sub.R. An operational amplifier 312 is employed in a feedback configuration to force the voltages on nodes 313 and 314 to be equal. The feedback signal of op-amp 312 is used to control the bias voltage of current sources 308-311. The current in sources 308 and 310 may be mirrored to an output terminal (not shown) in a conventional manner to provide a bias reference current I.sub.ref.
A diode-connected NPN transistor 306 biases transistor MN.sub.R at one V.sub.be below the supply voltage V.sub.cc, thereby forcing transistor MN.sub.R to operate in the triode region. A current source 311 sinks current from transistor 306. A diode-connected reference transistor MN.sub.ref is connected between V.sub.cc and the common base of NPN transistors 302 and 304 to bias the common base of transistors 302 and 304. The current in transistor MN.sub.ref is sunk by current source 309. Transistor MN.sub.ref is scaled to match the physical dimensions of transistor MN.sub.R.
The voltage on node 313 is equal to V.sub.cc minus the base-emitter voltage V.sub.BE of transistor 306 minus the gate-source voltage V.sub.GS of transistor MN.sub.R, i.e., EQU V.sub.313 =V.sub.cc -V.sub.BE(Q306) -V.sub.GS(MN.sbsb.R.sub.)
The voltage on node 314 is equal to V.sub.cc minus the gate-source voltage V.sub.GS of transistor MN.sub.ref minus the base-emitter voltage V.sub.BE of transistor 304, i.e., EQU V.sub.314 =V.sub.cc -V.sub.GS(MN.sbsb.ref.sub.) -V.sub.BE(Q304)
Equating the V.sub.BE 's of transistors Q304 and Q306 and rearranging terms gives EQU V.sub.GS(MN.sbsb.R.sub.) =V.sub.GS(MN.sbsb.ref.sub.)
In this manner, the V.sub.GS of transistor MN.sub.R, and thus the threshold V.sub.T and on-resistance R of transistor MN.sub.R, is set by reference transistor MN.sub.ref. Any process variations in transistor MN.sub.R are "mirrored" in and thus canceled by reference transistor MN.sub.ref, thereby allowing for the resistance R of transistor MN.sub.R to be substantially independent of process variations.
Since the operating points of transistors MN.sub.R and MN.sub.ref are in the linear and saturation regions, respectively, the drain current of transistor MN.sub.R may be expressed as: ##EQU1## where .beta. is substantially a constant. Noting that .DELTA.V.sub.BE is equal to the drain-source voltage V.sub.DS of transistor MN.sub.R, the drain current I.sub.D is substantially independent of the threshold voltage V.sub.T.
It is known that (i) the constant .beta. has a negative temperature coefficient (TC) approximately proportional to T.sup.-3/2, where T is the operating temperature, and (ii) V.sub.DS varies approximately with the operating temperature T. Thus, the current I.sub.D, as a whole, varies approximately with T.sup.1/2 and, thus, achieves a positive TC.
Although circuit 300 advantageously exhibits a positive temperature coefficient and substantially eliminates the dependence of transistor MN.sub.R 's resistance R upon process variations, circuit 300 consumes an undesirably large amount of current when generating small bias reference currents. For example, when configured to provide a reference bias current of 0.2 micro-amps, current sources 308-311 sink approximately 0.2, 0.4, 0.2, and 0.13 micro-amps, respectively, plus the current consumed by op-amp 312 (approximately 0.5 micro-amps). Accordingly, circuit 300 consumes almost 1.5 micro-amps of current to provide a reference bias current of just 0.2 micro-amps. Thus, it is desired to build a reference bias current generating circuit which not only is relatively insensitive to process variations and has a positive temperature coefficient but which also consumes a minimal amount of current.
Further, note that the minimum supply voltage required across circuit 300 is approximately 2.4 volts. That is, the base-emitter drop across transistor Q306 plus the gate-source voltage across transistor MN.sub.R plus the input common voltage required by op-amp 312, which is equal to the sum of a V.sub.BE and a V.sub.Dsat, equals approximately 2.4 volts. Therefore, circuit 300 is not capable of operating with voltage supplies of less than 2.4 volts. Thus, it would also be desirable to form a bias circuit which may be used with smaller supply voltages.